![]() ![]() The logical implication expression1 -> expression2 is logically equivalent to (!expression1 || expression2), and the logical equivalence expression1 expression2 is logically equivalent to ((expression1 -> expression2) & (expression2 -> expression1)).Ī_1 = 'b1 a_0 = 'b0 a_x = 'bx a_z = 'bz ī_1 = 'b1 b_0 = 'b0 b_x = 'bx b_z = 'bz ![]() SystemVerilog added two new logical operators logical implication (->), and logical equivalence ().
0 Comments
Leave a Reply. |
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |